1. Field of the Technology
The invention generally relates to frame processing techniques for the Synchronous Digital Hierarchy (SDH)/Synchronous Optical Network (SONET) and, more specifically, introduces a method and circuit for SDN/SONET frame alignment.
2. Background of the Invention
The SDH/SONET system is a signal transport system that transports signals at different rate levels on several standard-rate interfaces through an interleave multiplex and synchronous multiplex way. The SDH and the SONET are almost the same hierarchies except part of transmission rates and multiplexing paths are slightly different. Therefore, methods for the SDH system are introduced and those for the SONET system are completely same in principle. The ITU.T G707 has a detailed description of the SDH architecture.
FIG. 1 shows the rate hierarchy supported by the SDH system. FIG. 2 shows rates of Virtual Container with different rate levels and being supported by the SDH.
FIG. 3 shows the frame structure of SDH STM-1 (Synchronous Transport Module-1), in which the VC4s are formed by 63 VC12s.
The STM-2 frame is composed of 9 rows and 270 columns, namely totaling 2430 bytes, and takes 125 μs. Therefore, the rate of STM-1 in FIG. 1 is 155.520 Mbps. The first 9 columns of each frame are pointer addresses for RSOH (Regenerator Section Overhead), MSOH (Multiplexer Section Overhead) and AU-4 Pointer, and the rest 261 columns are for VC4. In the VC4, the first column is for Path Overhead (POH). When the VC4 is formed by 63 VC12s, the 8 columns that follow the POH column are the byte stuff columns, and the 252 columns that follow the stuff columns are formed by 63 TU12s that are multiplexed to TUG2s and then to TUG3s. See FIG. 9.
FIG. 4 shows the multiplexing paths defined by the G707 standard for different VC rates. In FIG. 4, the block with background color indicates pointer processing; the thick real line indicates multiplexing; the dot line indicates aligning and the thin real line indicates mapping.
During multiplexing, it often happens that the VC rate doesn't match the rates of the TU or AU to which the VC want to be multiplexed. In this case, the SDH deploys a pointer to locate the VC starting byte from a fixed position in the frame (the fixed position is the H3 byte for AU4, the H3 byte for TU3 and the V2 byte for TU1). The pointer value is adjusted with the positive justification and negative justification. For AU4, as shown in the FIG. 5, H1 and H2 are the pointers showing the starting byte of the VC-4, H3 is for negative justification and the three bytes after H3 is for positive justification. The FIG. 6 shows the TU3 pointer, and the FIG. 7 shows the TU12/TU11 pointer; wherein TU is the tributary unit, VC is the virtual container, V1 is the first byte of the pointer and V2 is the second byte of the pointer, V3 is the negative justification byte and V4 is a reserved byte.
FIGS. 8 and 9 show an interleaving processing where the TU11/TU12s are multiplexed into the TUG2s, and then the TUG2s are multiplexed into the TUG3s, and finally the TUG3s are multiplexed into the VC4.
The SDH multiplexing hierarchy defines a channel signal rate lower than VC4 as the lower order channel and a channel signal rate above the VC4 as the higher order channel. The lower order signals are interleaved into the TUG2s by columns, and then the TUG3s are interleaved into the TUG3s by columns, and then the TUG3s are interleaved into the VC4 by columns. When multiplexing lower order signals to a higher order virtual container, the pointer of the higher order virtual container needs to be adjusted for rate matching, so pointers of different higher order virtual containers may have different values. Therefore, before interleaving, the virtual containers need to be aligned. At present, the alignment is made with the method called Tributary Unit Payload Processor (TUPP).
From the ingress direction of a high order signal, the TUPP finds the pointers of the lower order signals. With interpretation of a lower order signal pointer, the lower order signal payload is obtained and stored in an FIFO queue. Later, based on aligning requirement, the timing signal is generated. With the timing signal, the FIFO output is controlled and a new pointer justification is generated. The payloads of lower order signals in the FIFO and the generated pointers form an aligned high order signal that is the egress signal of the TUPP.
Taking the lower order traffic TU12 as an example, shown in FIG. 10, the Receiving Timer and Transmitting Timer generate necessary timing signals; the pointer interpreters (PI) of the modules 1, 2, . . . 63 make pointer interpretation of each channel respectively to obtain the payload position of each channel; under the control of the RecTiming signal, the payloads are stored in the First-In-First-Out (FIFO) memories; the Pointer Generator modules PG1, PG2, . . . PG63 generate new pointers for each channel; and the Multiplexing module regenerates the payloads and their new pointers that are aligned for the higher order signal VC4.
The alignment processing of the TU11, TU3 or payloads mapped by them is similar as above.
The above method meets demands of system for lower order signals in early SDH/SONET development phase when the system capacity is limited; However, with increase of system demands for lower order traffic, the method can hardly meet market needs. The TUPP is implemented by an ASIC on usual, and each ASIC can only process several channels, which leads to many ASICs in system. This makes serial problems for the system, such as system complexity increase, power consumption rising, system integration and system stability decrease etc.